MT9V024/D

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32

Table 18. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Minimum

Maximum

Unit

Power supply voltage (all supplies)

–0.3

4.5

V

Total power supply current

–

200

mA

Total ground current

–

200

mA

DC input voltage

–0.3

V

DC output voltage

–0.3

V

Storage temperature

–50

+150

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

7. This is a stress rating only, and functional operation of the device at these other conditions above those indicated in the operational sections

of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Symbol

Definition

Condition

Minimum

Typical

Maximum

Unit

SYSCLK

Input Clock Frequency

13.0

26.6

27.0

MHz

Clock Duty Cycle

45.0

50.0

55.0

%

Input Clock Rise Time

–

3

5

ns

Input Clock Fall Time

–

3

5

ns

SYSCLK to PIXCLK Propagation Delay

4

6

8

ns

–3

0.6

3

ns

Data Setup Time

14

16

–

ns

Data Hold Time

14

16

–

PIXCLK to LV Propagation Delay

5

7

9

ns

PIXCLK to FV Propagation Delay

5

7

9

ns

Propagation Delays for PIXCLK and Data Out Signals

The pixel clock is inverted and delayed relative to the

master clock. The relative delay from the master clock

(SYSCLK) rising edge to both the pixel clock (PIXCLK)

falling edge and the data output transition is typically 7 ns.

Note that the falling edge of the pixel clock occurs at

approximately the same time as the data output transitions.

See Table 19 for data setup and hold times.

Figure 38. Propagation Delays for PIXCLK and Data Out Signals

t

tR

tF

SYSCLK

PIXCLK

tHD

SD

tPD

PD