WM8501

Pre-Production

w

PP Rev 3.1 May 2006

6

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analogue supply range

AVDD

4.5

5.5

V

Digital supply range

DVDD

2.7

5.5

V

Ground

AGND, DGND

0

V

Analog supply current

AVDD = 5V

9

mA

Digital supply current

DVDD = 5V

8

mA

DVDD = 3.3V

4.5

mA

Power down current (note 4)

AVDD=DVDD=5V

0.01

mA

ELECTRICAL CHARACTERISTICS

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Logic Levels (TTL Levels)

Input LOW level

0.8

V

Input HIGH level

2.0

V

Output LOW

DGND + 0.3V

V

Output HIGH

DVDD – 0.3V

V

Analogue Reference Levels

Reference voltage (VMID)

AVDD/2

V

Potential divider resistance

AVDD to VMID and

VMID to GND

50

k

Ω

DAC Output (Load = 10k

Ω

Ω

Ω

Ω. 50pF)

0dBFs Full scale output voltage

At DAC outputs

1.6 x

AVDD/5

1.7 x

AVDD/5

1.8 x

AVDD/5

Vrms

A-weighted,

@ fs = 48kHz

90

100

dB

A-weighted

@ fs = 96kHz

97

dB

Signal to Noise Ratio (Note

5,6,7)

SNR

A-weighted

@ fs = 192kHz

97

dB

Dynamic Range (Note 2, 6)

DNR

A-weighted, -60dB full

scale input

90

100

dB

Total Harmonic Distortion

(Note 7)

THD

1kHz, Load = 10k

Ω,

0dBFS

-88

-78

dB

DAC channel separation

93

dB

Analogue Output Levels

Output level

Load = 10k

Ω, 0dBFS

1.7

Vrms

Gain mismatch

channel-to-channel

±1

%FSR

Minimum resistance load

To midrail or a.c.

coupled

16

Ω

Output d.c. level

AVDD/2

V

Notes:

1.

Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

2.

All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a

filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics.

The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

3.

VMID pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

4.

Power down occurs 1.5

µs after MCLK is stopped.