FXLS8964AF datasheet(96/98 Pages) NXP

96 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

Tab. 115. SDCD_UTHS_MSB register (address 36h)

bit description .................................................. 78

Tab. 116. SELF_TEST_CONFIG1 register (address

37h) bit allocation ............................................78

Tab. 117. SELF_TEST_CONFIG1 register (address

37h) bit description ..........................................78

Tab. 118. SELF_TEST_CONFIG2 register (address

38h) bit allocation ............................................78

Tab. 119. SELF_TEST_CONFIG2 register (address

38h) bit description ..........................................79

Tab. 120. Self-Test measurement phase decimation

settings ............................................................ 79

Tab. 121. Glossary .......................................................... 89

Tab. 122. Revision history ...............................................91

Figures

Fig. 1.

Block Diagram ...................................................3

Fig. 2.

Pin configuration diagram ................................. 4

Fig. 3.

Sensitive axes orientation and output

response to ±1 g (gravity) stimulus ................... 6

Fig. 4.

I2C secondary timing diagram for

Standard-mode, Fast-mode and Fast-mode

Plus ................................................................. 14

Fig. 5.

I2C Data Sequence Diagrams ........................ 16

Fig. 6.

SPI single-byte write protocol diagram (3-

or 4-wire mode), R/W = 0 ............................... 17

Fig. 7.

SPI multiple-byte write protocol diagram (3-

or 4-wire mode), R/W = 0 ............................... 17

Fig. 8.

SPI single-byte read protocol diagram (4-

wire mode), R/W = 1 .......................................18

Fig. 9.

SPI multiple-byte read protocol diagram (4-

wire mode), R/W = 1 .......................................18

Fig. 10.

SPI single-byte read protocol diagram (3-

wire mode) ...................................................... 18

Fig. 11.

SPI multiple-byte read protocol diagram (3-

wire mode) ...................................................... 19

Fig. 12.

SPI timing diagram (4-wire mode) ...................20

Fig. 13.

SPI timing diagram (3-wire mode) ...................21

Fig. 14.

Operating modes transition diagram ............... 23

Fig. 15.

BOOT2 sequence and One-wire motion-

detection protocol diagram (BT_MODE =

VDD) ................................................................25

Fig. 16.

BOOT1 sequence (BT_MODE = GND) ...........27

Fig. 17.

SDCD Function Block Diagram .......................69

Fig. 18.

SDCD REF_UPD timing diagram ....................75

Fig. 19.

Typical Application Circuit #1 – I2C mode ....... 81

Fig. 20.

Typical Application Circuit #2 – SPI 4-wire

mode ............................................................... 81

Fig. 21.

Typical Application Circuit #3 – SPI 3-

wire mode (software enabled; SENS_

CONFIG1[SPI_M] = 1) .................................... 81

Fig. 22.

Typical Application Circuit #4 – SPI 3-wire

mode (hardwired; SENS_CONFIG1[SPI_

M] = X) ............................................................82

Fig. 23.

Typical Application Circuit #5 – Motion

detection mode (no serial interface) ................82

Fig. 24.

Typical Application Circuit #6 - Motion

detection mode (with SPI 3-wire interface,

software enabled) ............................................82

Fig. 25.

FXLS8964AF package outline .........................84

Fig. 26.

FXLS8964AF package outline detail ............... 85

Fig. 27.

FXLS8964AF package outline notes ...............86

Fig. 28.

Bottom and leaded view dimensions ...............87

Fig. 29.

PCB footprint guidelines ..................................89

FXLS8964AF

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Product data sheet

Rev. 3.4 — 7 December 2021

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FXLS8964AF Datasheet(PDF) 96 Page - NXP Semiconductors

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