AMT49106 datasheet(22/74 Pages) ALLEGRO

22 / 74 page

Automotive Three-Phase MOSFET Driver

AMT49106

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Input and Output Terminal Functions

VBB: Power supply for VREG charge pump regulator. Should be

connected to VBB through a reverse voltage protection circuit

and should be decoupled with ceramic capacitors connected close

to the supply and ground terminals.

CP1, CP2, CP3, CP4: Pump capacitor connections for VREG

charge pump. Connect capacitors with a recommended nominal

value of 2.2 µF between CP1 and CP2 and between CP3 and

CP4. These devices should have a rated working voltage of at

least 50 V and a tolerance of ±20% or better.

CP5, CP6: Pump capacitor connection for external VCP charge

pump. Connect a capacitor with a recommend nominal value of

2.2 µF between CP5 and CP6. This device should have a rated

working voltage of at least 25 V and a tolerance of ±20% or bet-

ter.

VREG: Regulated output voltage, used to supply the low-side

gate drivers and to charge the bootstrap capacitors. A sufficiently

large storage capacitor must be connected between this terminal

and the GND terminal to provide the transient charging current.

GND: Ground. See Layout Recommendations section for further

information.

CA, CB, CC: High-side connections for the bootstrap capacitors

and positive supply for high-side gate drivers.

GHA, GHB, GHC: High-side gate drive outputs for external

N-channel MOSFETs.

SA, SB, SC: Load phase connections. These terminals are the

negative supply connections for the floating high-side drivers and

are also connected to the negative side of the bootstrap capaci-

tors.

GLA, GLB, GLC: Low-side gate drive outputs for external

N-channel MOSFETs.

LSSA, LSSB, LSSC: Low-side return path for discharge of

the capacitance on the MOSFET gates, connected to the com-

mon sources of the low-side external MOSFETs independently

through a low impedance track.

HA, HB, HC: Logic inputs to control the high-side gate drive

outputs. Battery voltage compliant terminal.

LA, LB, LC: Logic inputs to control the low-side gate drive out-

puts. Battery voltage compliant terminal.

SDI: Serial data logic input with pull-down. 16-bit serial word

input MSB first.

SDO: Serial data output. High impedance when STRn is high.

Outputs bit 15 of the Status register, the fault flag, as soon as

STRn goes low.

SCK: Serial clock logic input with pull-down. Data is latched

in from SDI on the rising edge of SCK. There must be 16-rising

edges per write and SCK must be held high when STRn changes.

STRn: Serial data strobe and serial access enable logic input

with pull-up. When STRn is high, any activity on SCK or SDI

is ignored and SDO is high impedance, allowing multiple SDI

slaves to have common SDI, SCK, and SDO connections.

CS1P, CS1M, CS2P, CS2M, CS3P, CS3M: Current sense ampli-

fier inputs.

CS1O, CS2O, CS3O: Current sense amplifier outputs.

DIAG: Diagnostic output. Programmable output to provide one

of four functions: fault flag, pulsed fault flag, temperature, or

internal timer. Default is fault flag.

OOR: Power supply for current sense amplifier output stages.

Voltage applied to this pin,VOOR, internally divided by a factor of

two to generate the current sense amplifier output offset voltage,

VOOS.

ENABLE: Disables all gate drive outputs when pulled low.

Provides an independent output disable, directly to the gate drive

outputs, to allow a fast disconnect on the power bridge. Battery

voltage compliant terminal.

VCP: Pumped gate drive voltage referenced to the VBB terminal.

Can be used to bias external circuitry in accordance with the VCP

voltage specification in the Electrical Characteristics table. Con-

nect a ceramic capacitor, CVCP, of nominal value 2.2 µF between

VCP and VBB. This device should have a rated working voltage

of at least 25 V and a tolerance of ±20% or better.

VIO: Logic I/O and core logic supply input. Sets logic input

thresholds and powers all digital functions including the SPI

interface.

AMT49106 Datasheet(PDF) 22 Page - Allegro MicroSystems

AMT49106 Datasheet(HTML) 22 Page - Allegro MicroSystems

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