35 / 43 page

DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
35
Version: DM9101-DS-F03
July 22, 1999
MII-10Base-T Nibble Transmit Timing Diagram
TX_CLK
tTX
h
t2
tTX
S
t1
tTX
pd
TXD [0:3],
TX_EN, TX_ER
CRS
10TX+/-
MII-10Base-T Nibble Transmit Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tTX
s
TXD[0:3), TX_EN, TX_ER Setup
To TX_CLK High
11
-
-
ns
tTX
h
TXD[0:3], TX_EN, TX_ER Hold
From TX_CLK High
0-
-
ns
t1
TX_EN Sampled To CRS
Asserted
-2
4
BT
t2
TX_EN Sampled To CRS De-
asserted
-15
20
BT
tTX
pd
TX_EN Sampled To 10TXO Out
(Tx Latency)
-2
4
BT
MII-10Base-T Receive Nibble Timing Diagram
RX_CLK
t2
t1
tTX
pd
RXD [0:3],
RX_DV, RX_ER
CRS
RXI+/-
tRX
S
tRX
h
t4
t3