8 Detailed Description

8.1 Overview

The TCAL9539 digital core consists of 8-bit data registers which allow the user to configure the I/O port

characteristics. At power on or after a reset, the I/Os are configured as inputs. However, the system controller

can configure the I/Os as either inputs or outputs by writing to the Configuration registers. The data for each

input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port

register can be inverted with the Polarity Inversion register. All registers can be read by the system controller.

Additionally, the TCAL9539 has Agile I/O functionality which is specifically targeted to enhance the I/O ports.

The Agile I/O features and registers include programmable output drive strength, programmable pull-up and

pull-down resistors, latchable inputs, maskable interrupts, interrupt status register, and programmable open-drain

or push-pull outputs. These configuration registers improve the I/O by increasing flexibility and allowing the user

to optimize their design for power consumption, speed, and EMI.

Other features of the device include an interrupt that is generated on the INT pin whenever an input port

changes state. The device can be reset to its default state by applying a low logic level to the RESET pin, issuing

a software reset command, or by cycling power to the device and causing a power-on reset. The hardware

The TCAL9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system controller that an input state has changed. The INT

pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the device

can inform the processor if there is incoming data on the remote I/O ports without having to communicate via the

The system controller can reset the device in the event of a timeout or other improper operation by asserting a

POR cause the same reset/initialization to occur, but the RESET feature does so without needing to power down

the device.

8.2 Functional Block Diagrams

Input

Filter

I2C Bus

Control

Shift

Register

16 Bits

I/O

Port

P00-P07

Power-On

Reset

SCL

SDA

GND

Write Pulse

Read Pulse

Interrupt Logic

INT

RESET

P10-P17

A0

A1

A.

All I/Os are set to inputs at reset.

Figure 8-1. Logic Diagram (Positive Logic)

www.ti.com

TCAL9539

SCPS241 – JULY 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: TCAL9539