3

TDM interface characteristics

All setup times and hold times in Table 5 and in Figure 2 are valid for BCLK polarity set to “clock on rising”.

If BCLK polarity is set to “clock on falling”, then all setup and hold times will refer to the falling edge of BCLK

instead. Please refer to Section 4 TDM interface specifications for additional details.

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

MCLK

MCLK frequency nominal

12.288

MHz

MCLKA

MCLK frequency accuracy

-0.1

0.1

%

MCLKJ

MCLK jitter

1

ns (peak to peak)

BCLK

BCLK frequency (1/tp)

in disabled mode

MCLK

MHz

WCLK = 8 kHz

1.024

MHz

WCLK = 16 kHz

2.048

MHz

WCLK = 24 kHz

3.072

MHz

WCLK8

8 kHz WCLK mode

8

kHz

WCLK16

16 kHz WCLK mode

16

WCLK24

24 kHz WCLK mode

24

PDC

All clock pin duty cycle

(except WCLK)

45

55

%

WT

WCLK setup time before BCLK rising/falling edge (tss1)

20

ns

SDOST

SDOUT setup time before BCLK rising/falling edge (tss2)

15

ns

SDOHTR SDOUT hold time after BCLK rising/falling edge (ths1)

15

ns

SDOHTZ

SDOUT hold time of LSB after BCLK rising/falling edge (ths2)

15

50

ns

MCLK pin capacitance

10

pF

BCLK pin capacitance

10

VCLK pin capacitance

10

SDOUT load capacitance

60

Relative frequency response(1)

(2)

-0.5

0.4

dB

1. Data by simulation

2. All the DUT measurement points are normalized to the 294 Hz measurement. The deviation between each point and 294 Hz is calculated.

AIS25BA

TDM interface characteristics

DS14019 - Rev 1

page 6/31