ZSC31050 Datasheet

© 2022 Renesas Electronics Corporation

23

January 14, 2022

Figure 7. Application Example 5

Two-wire 4mA to 20mA configuration (7 to 48 V), temperature compensation via internal diode

Sensor Bridge

2

1

3

4

6

5

7

8

15

16

14

13

11

12

10

9

VDDA

IN3

VGATE

IO1

IO2

SCL

SDA

VDD

VINN

VSS

VINP

VBR

IR_TEMP

FBP

OUT

FBN

SCL

SDA

GND

ZD

7.5V

150

Ω

50

Ω

VDDA = 5V

+7V to +48V

IO1

IO2

C2

0.1µF

C3

10nF

C1

0.1µF

(Current Loop+)

(Current Loop)

Serial Interface

Flexible I/Os

2.2k

Ω

C4

220pF

Note: It is possible to combine or separate connectivity of different application examples. For VDD generation, Renesas recommends using the

internal supply voltage regulator with an external capacitor. Refer the ZSC31050 Application Note—Current Loop for use of supply voltage

regulation features (non-ratiometric mode) and current loop output mode.

4. ESD/Latch-Up-Protection

All pins have an ESD protection of >2000V, except the VINN, VINP, and FBP pins, which have an ESD protection >1200V. All pins have a

latch-up protection of

100mA or +8V/ –4V (relative to VSS/VSSA). Refer to section 5 for details and restrictions. ESD protection referenced to

the Human Body Model is tested with devices in 16-SSOP packages during product qualification. The ESD test follows the Human Body Model

with 1.5kOhm/100pF based on MIL 883, method 3015.7.