RT8249 datasheet(22/23 Pages) RICHTEK

22 / 23 page

RT8249A/B/C

DS8249A/B/C-02

June 2014

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Output Capacitor Selection

The capacitor value and ESR determine the amount of

output voltage ripple and load transient response. Thus,

the capacitor value must be greater than the largest value

calculated from the equations below :

LOAD

OFF(MIN)

SAG

OUT

OUTx

OFF(MIN)

)

L (t

+ t

)

+ t

)

 













()

LOAD

SOAR

OUT

OUTx







P P

LOAD(MAX)

OUT

LIR I

ESR +













where VSAG and VSOAR are the allowable amount of

undershoot and overshoot voltage during load transient,

Vp-p is the output ripple voltage, and tOFF(MIN) is the

minimum off-time.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WQFN-20L 3x3 package, the thermal resistance,

θJA, is

°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25

°C can

be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (30°C/W) = 3.33W for

WQFN-20L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 8 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 8. Derating Curve of Maximum Power Dissipation

Layout Considerations

Layout is very important in high frequency switching

converter design. Improper PCB layout can radiate

excessive noise and contribute to the converter’s

instability. Certain points must be considered before

starting a layout with the RT8249A/B/C.



Place the filter capacitor close to the IC, within 12mm

(0.5 inch) if possible.



Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high-voltage switching node.



Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.



All sensitive analog traces and components such as

FBx, PGOOD, and should be placed away from high

voltage switching nodes such as PHASEx, LGATEx,

UGATEx, or BOOTx nodes to avoid coupling. Use

internal layer(s) as ground plane(s) and shield the

feedback trace from power traces and components.



Place ground terminal of VIN capacitor(s), VOUTx

capacitor(s), and Source of low-side MOSFETs as close

to each other as possible. The PCB trace of PHASEx

node, which connects to Source of high-side MOSFET,

Drain of low-side MOSFET and high voltage side of the

inductor, should be as short and wide as possible.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

RT8249 Datasheet(PDF) 22 Page - Richtek Technology Corporation

RT8249 Datasheet(HTML) 22 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL