HT45R06 datasheet(16/41 Pages) HOLTEK

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HT45R06

Rev. 1.00

May 24, 2005

After a chip reset, these input/output lines remain at high

levels or floating state (depending on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest 7-bit of port D and 4 bits of port B

are not physically implemented, on reading them a

²0² is

returned whereas writing then results in no-operation.

See Application note.

There is a pull-high option available for all I/O lines.

Once the pull-high option is selected, all I/O lines have

pull-high resistors. Otherwise, the pull-high resistors are

absent. It should be noted that a non-pull-high I/O line

operating in input mode will cause a floating state.

The PA3 is pin-shared with the PFD. If the PFD option is

selected, the output signal in output mode of PA3 will be

the PFD signal generated by the timer/event counter

overflow signal. Those in the input mode always main-

tain their original functions. Once the PFD option is se-

lected, the PFD output signal is controlled by PA3 data

²1² to PA3 data register will enable

the PFD output function and writing

²0² will force the

PA3 to remain at

²0². The I/O functions of PA3 are

shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The PA4 and PA5 are pin-shared with TMR and INT pins

respectively.

The PB can also be used as A/D converter inputs. The

A/D function will be described later.

A/D Converter

The 4 channels and 8-bit resolution A/D converter are

implemented in this microcontroller. The reference volt-

age is VDD. The A/D converter contains three special

registers, namely, ADR (21H), ADCR (22H) and ACSR

(23H). The ADR is A/D result register and is read-only.

After the A/D conversion is completed, the ADR should

be read to retrieve the conversion result data. The

ADCR is an A/D converter control register, which de-

fines the A/D channel number, analog channel select,

start A/D conversion control bit and end of A/D conver-

sion flag. If users want to start an A/D conversion, they

should define the PB configuration, select the converted

analog channel, and give START bit a raising edge and

falling edge (0

®1®0). At the end of A/D conversion, the

EOCB bit is cleared and an A/D converter interrupt oc-

curs (if the A/D converter interrupt is enabled). The

ACSR is A/D clock setting register, which is used to se-

lect the A/D clock source.

The A/D converter control register is used to control the

A/D converter. The bit2~bit0 of the ADCR are used to

select an analog input channel. There are a total of eight

channels to select. The bit5~bit3 of the ADCR are used

to set PB configurations. PB can be an analog input or

as digital I/O line determined by these 3 bits. Once a PB

line is selected as an analog input, the I/O functions and

pull-high resistor of this I/O line are disabled and the A/D

converter circuit is powered on. The EOCB bit (bit6 of

the ADCR) is end of A/D conversion flag. Check this bit

to know when A/D conversion is completed. The START

bit of the ADCR is used to begin the conversion of the

A/D converter. Giving START bit a rising edge and fall-

ing edge means that the A/D conversion has started. In

order to ensure that A/D conversion is completed, the

START should remain at

²0² until the EOCB is cleared to

²0² (end of A/D conversion).

The bit 7 of the ACSR is used for testing purposes only.

It cannot be used by the users. The bit1 and bit0 of the

ACSR are used to select the A/D clock sources.

Bit No.

Label

Function

ADCS0

ADCS1

Selects the A/D converter clock source

00=system clock/2

01=system clock/8

10=system clock/32

11=undefined

2~6

Unused bit, read as

²0²

TEST

For test mode used only

ACSR (23H) Register

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