HT46R232 datasheet(26/50 Pages) HOLTEK

26 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

Start Signal

The START signal is generated only by the master de-

vice. The other device in the bus must detect the START

signal to set the I

2C Bus busy bit (HBB). The START sig-

nal is SDA line from high to low, when SCL is high.

Slave Address

The master must select a device for transferring the

data by sending the slave device address after the

START signal. All device in the I

2C Bus will receive the

2C Bus slave address (7 bits) to compare with its own

slave address (7 bits). If the slave address is matched,

the slave device will generate an interrupt and save the

following bit (8th bit) to SRW bit and sends an acknowl-

edge bit (low level) to the 9th bit. The slave device also

sets the status flag (HAAS), when the slave address is

matched.

In interrupt subroutine, check HAAS bit to know whether

the I

2C Bus interrupt comes from a slave address that is

matched or a data byte transfer is completed. When the

slave address is matched, the device must be in trans-

mit mode or receive mode and write data to HDR or

dummy read from HDR to release the SCL line.

SRW Bit

The SRW bit means that the master device wants to

read from or write to the I

2C Bus. The slave device

check this bit to understand itself if it is a transmitter or a

receiver. The SRW bit is set to

²1² means that the mas-

ter wants to read data from the I

2C Bus, so the slave de-

vice must write data to a bus as a transmitter. The SRW

is cleared to

²0² means that the master wants to write

data to the I

2C Bus, so the slave device must read data

from the I

2C Bus as a receiver.

Acknowledge Bit

One of the slave device generates an acknowledge signal,

when the slave address is matched. The master device

can check this acknowledge bit to know if the slave device

accepts the calling address. If no acknowledge bit, the

master must send a STOP bit and end the communication.

When the I

2C Bus status register bit 6 HAAS is high, it

means the address is matched, so the slave must check

SRW as a transmitter (set HTX) to

²1² or as a receiver

(clear HTX) to

²0².

Data Byte

The data is 8 bits and is sent after the slave device has

acknowledged the slave address. The first bit is MSB

and the 8th bit is LSB. The receiver sends the acknowl-

edge signal (

²0²) and continues to receive the next one

byte data. If the transmitter checks and there

¢snoac-

knowledge signal, then it release the SDA line, and the

master sends a STOP signal to release the I

2C Bus. The

data is stored in the HDR register. The transmitter must

write data to the HDR before transmitting data and the

receiver must read data from the HDR after receiving

data.

Receive Acknowledge Bit

When the receiver wants to continue to receive the next

data byte, it generates an acknowledge bit (TXAK) at

the 9th clock. The transmitter checks the acknowledge

bit (RXAK) to continue to write data to the I

2C Bus or

change to receive mode and dummy read the HDR reg-

ister to release the SDA line and the master sends the

STOP signal.

S C L

S D A

S t a r t b i t

D a t a

s t a b l e

D a t a

a l l o w

c h a n g e

S t o p b i t

Data Timing Diagram

S C L

S D A

Start Bit

S C L

S D A

Stop Bit

HT46R232 Datasheet(PDF) 26 Page - Holtek Semiconductor Inc

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