MN89201

For Information Equipment

Pin Descriptions

Pin No.

Symbol

I/O

Function Description

3

AEN

I

Chip select signal

"L" level: Register access enabled

"H" level: Register access disabled

4

XRD

I

Read control signal

"L" level: Read enabled

5

XWE

I

Write control signal

"L" level: Write enabled

6

REGLIN

I

Register address mode specification

"H" level: Obtain register address from RA[3:0]

"L" level: Obtain register address from address register

In the latter case, the address of the parameter/mode register are

specified by the address register .

Address register: 0H (4-bit decode)

Data register:

1H (4-bit decode)

7 to 10

RA[3:0]

I

Register address specification

11 to 14

DB[7:0]

I

Host data bus

17 to 20

23

RESET

I

MN89201 reset signal

Active "H"

This signal initializes internal registers to their default values and

resets internal synchronization counters.

24 ,25

MODSET[1:0]

I

Synchronization mode specification pins

These specify the RDCLK synchronization mode for output signals

to the NTSC encoder

(1:0)

0 0: Use an external VCO clock signal synchronized with the VGA

clock signal for RDCLK. The XH, XVSYNC, XBLANK, and

XENRST signals are generated inside the MN89201 and are

outputted. (synchronous)

0 1: Use an external oscillator clock signal not synchronized with

the VGA clock signal for RDCLK. The XH and XVSYNC

signals are retimed versions of the VGA H and VSYNC

signals. (asynchronous)

The other outputs use the VGA DOTCLK signal.

1 0: Use the VGA DOTCLK signal for RDCLK. The YCrCb data,

XVSYNC, XBLANK, and XENRST signals all are dealt in

the VGA clock. An external oscillator is not necessary.

(synchronous)