Advanced CMOS TTL Input – 74ACT00

Quad 2-Input NAND Gates with LSTTL compatible inputs in bare die form

Rev 1.0

18/05/21

Die Size (Unsawn)

1200 x 1200

47 x 47

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si



Inputs directly accept TTL



Outputs directly interface CMOS, NMOS and TTL



Outputs Source/Sink 24 mA



Low Input Current: 1µA



Functionally compatible with bipolar 74LS00



Performance improvement versus 74HCT00



Lower power alternative to bipolar logic.

Features:

Ordering Information

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection

For High Reliability versions of this product please see

54ACT00

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (400 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 350µm(14 Mils) – On request



Assembled into Ceramic Package – On request

The 54ACT00 quad 2-input NAND gates is fabricated on

a 1.5µm advanced CMOS process combining high

speed LSTTL performance with CMOS low power. The

device consists of x4 independent 2-input NAND gates

performing the Boolean function Y = A • B or Y = A + B.

Internal circuitry comprises of three stages and includes

buffered output for high noise immunity and stability.

Inputs are directly compatible with LSTTL outputs. All

inputs are protected against ESD and excess voltage

transients.

Description

Die Dimensions in µm (mils)

1200 (47.24)

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