PAL16R82 datasheet(33/33 Pages) AMD

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AMD

2-35

PAL16R8 Family

POWER-UP RESET

The power-up reset feature ensures that all flip-flops will

be reset to LOW after the device has been powered up.

The output state will be HIGH due to the inverting output

buffer. This feature is valuable in simplifying state

machine initialization. A timing diagram and parameter

table are shown below. Due to the synchronous opera-

tion of the power-up reset and the wide range of ways

VCC can rise to its steady state, two conditions are

required to ensure a valid power-up reset. These condi-

tions are:

s The VCC rise must be monotonic.

s Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and feed-

back setup times are met.

Parameter

Symbol

Parameter Description

Max

Unit

tPR

Power-Up Reset Time

1000

Input or Feedback Setup Time

tWL

Clock Width LOW

tPR

tWL

4 V

VCC

Power

Registered

Active-Low

Output

Clock

16492D-31

See Switching

Characteristics

Power-Up Reset Waveform

PAL16R82 Datasheet(PDF) 33 Page - Advanced Micro Devices

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