WM8786GEDSSLASHV datasheet(8/22 Pages) WOLFSON

Part #	WM8786GEDS/V

Description	24-Bit, 192kHz Stereo ADC

PDF	22 Pages

Scroll/Zoom	100%

Manufacturer	WOLFSON [Wolfson Microelectronics plc]

Direct Link	http://www.wolfsonmicro.com

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8 / 22 page

WM8786

Pre-Production

PP Rev 3.0 December 2005

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock cycle time

TMCLKY

MCLK duty cycle

TMCLKDS

60:40

40:60

AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25

oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

tDL

DOUT propagation delay from BCLK falling edge

tDDA

WM8786GEDS/V Datasheet(PDF) 8 Page - Wolfson Microelectronics plc