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DS320PR822 Datasheet(PDF) 21 Page - Texas Instruments |
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DS320PR822 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 38 page ![]() Table 7-8. DEVICE_ID0 Register (Offset = 0xF0) (continued) Bit Field Type Reset Description 1 device_id0_1 R 0x1 see MSB 0 RESERVED R X Reserved Table 7-9. DEVICE_ID1 Register (Offset = 0xF1) Bit Field Type Reset Description 7 device_id[7] R 0x0 Device ID 0010 1001: DS320PR822 6 device_id[6] R 0x0 see MSB 5 device_id[5] R 0x1 see MSB 4 device_id[4] R 0x0 see MSB 3 device_id[3] R 0x1 see MSB 2 device_id[2] R 0x0 see MSB 1 device_id[1] R 0x0 see MSB 0 device_id[0] R 0x0 see MSB 7.5.2.2 Channel Registers Table 7-10. RX Detect Status Register (Channel Register Base + Offset = 0x00) Bit Field Type Reset Description 7 rx_det_comp_p R 0x0 Rx Detect positive data pin status: 0: Not detected 1: Detected – the value is latched 6 rx_det_comp_n R 0x0 Rx Detect negative data pin status: 0: Not detected 1: Detected – the value is latched 5-0 RESERVED R 0x0 Reserved Table 7-11. EQ Gain Control Register (Channel Register Base + Offset = 0x01) Bit Field Type Reset Description 7 eq_stage1_bypass R/W 0x0 Enable EQ stage 1 bypass: 0: Bypass disabled 1: Bypass enabled 6 eq_stage1_3 R/W 0x0 EQBoost stage 1 control See Table 7-1 for details 5 eq_stage1_2 R/W 0x0 4 eq_stage1_1 R/W 0x0 3 eq_stage1_0 R/W 0x0 2 eq_stage2_2 R/W 0x0 EQ Boost stage 2 control See Table 7-1 for details 1 eq_stage2_1 R/W 0x0 0 eq_stage2_0 R/W 0x0 Table 7-12. EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03) Bit Field Type Reset Description 7 RESERVED R 0x0 Reserved 6 eq_profile_3 R/W 0x0 EQ mid-frequency boost profile See Table 7-1 for details 5 eq_profile_2 R/W 0x0 4 eq_profile_1 R/W 0x0 3 eq_profile_0 R/W 0x0 www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DS320PR822 |
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