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DS320PR810NJXT Datasheet(PDF) 20 Page - Texas Instruments |
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DS320PR810NJXT Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 38 page  Table 7-11. EQ Gain Control Register (Channel register base + Offset = 0x01) (continued) Bit Field Type Reset Description 6 eq_stage1_3 R/W 0x0 EQBoost stage 1 control See Table 7-1 for details 5 eq_stage1_2 R/W 0x0 4 eq_stage1_1 R/W 0x0 3 eq_stage1_0 R/W 0x0 2 eq_stage2_2 R/W 0x0 EQ Boost stage 2 control See Table 7-1 for details 1 eq_stage2_1 R/W 0x0 0 eq_stage2_0 R/W 0x0 Table 7-12. EQ Gain / Flat Gain Control Register (Channel register base + Offset = 0x03) Bit Field Type Reset Description 7 RESERVED R 0x0 Reserved 6 eq_profile_3 R/W 0x0 EQ mid-frequency boost profile See Table 7-1 for details 5 eq_profile_2 R/W 0x0 4 eq_profile_1 R/W 0x0 3 eq_profile_0 R/W 0x0 2 flat_gain_2 R/W 0x1 Flat gain select: See Table 7-2 for details 1 flat_gain_1 R/W 0x0 0 flat_gain_0 R/W 0x1 Table 7-13. RX Detect Control Register (Channel register base + Offset = 0x04) Bit Field Type Reset Description 7-3 RESERVED R 0x0 Reserved 2 mr_rx_det_man R/W 0x0 Manual override of rx_detect_p/n decision: 0: rx detect state machine is enabled 1: rx detect state machine is overridden – always valid RX termination detected 1 en_rx_det_count R/W 0x0 Enable additional RX detect polling 0: Additional RX detect polling disabled 1: Additional RX detect polling enabled 0 sel_rx_det_count R/W 0x0 Select number of valid RX detect polls – gated by en_rx_det_count = 1 0: Device transmitters poll until 2 consecutive valid detections 1: Device transmitters poll until 3 consecutive valid detections Table 7-14. PD Override Register (Channel register base + Offset = 0x05) Bit Field Type Reset Description 7 device_en_override R/W 0x0 Enable power down overrides thorugh SMBus/I2C 0: Manual override disabled 1: Manual override enabled 6-0 device_en R/W 0x111111 Manual power down of redriver various blocks – gated by device_en_override = 1 111111: All blocks are enabled 000000: All blocks are disabled Table 7-15. Bias Register (Channel register base + Offset = 0x06) Bit Field Type Reset Description 5-3 Bias current R/W 0x100 Control bias current Set 001 for best performance DS320PR810 SNLS668 – AUGUST 2022 www.ti.com 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DS320PR810 |
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