L9654 datasheet(49/59 Pages) STMICROELECTRONICS

49 / 59 page

DocID14218 Rev 3

49/59

L9654

Functional description

4.14.6

FIFO buffer

The IC includes 2 internal FIFO buffers; one for each output channel, each one is 12 bits

and two levels deep. When D1 in the MCR register is set to 0 (default condition), MSG pin is

asserted and remains asserted as long as there is a message in any of the 2 internal FIFO

buffers.

The FIFO provides error flag via SPI in case of buffer data loss. When writing to a full FIFO

the old data is lost. For example if the FIFO content at the bottom of the stack is $0AA, an

incoming message of $090 occupies the upper level of the FIFO stack, at this stage the

FIFO is full, but the Data lost flag is not set. When writing another message to the FIFO, for

example $066, the Data lost flag is set and the final FIFO content is $066 (top of stack) and

$090(bottom of stack). When a FIFO read operation is performed via SPI, The FIFO content

$090 is carried over by MISO and Data lost flag is unset. The Data lost flag is also unset

when the FIFO is flushed via SPI command.

4.14.7

Satellite continuity check

Each output has a short circuit protection by independent current limit. When a short circuit

occurs the output becomes current limited, a fault timer latches the output off and a fault

condition bit is reported via SPI.

That output returns to normal operation when it is re-enabled via SPI and the current limit

condition was removed, this fault condition does not interfere with the operation of any of the

other output channels

4.14.8

Message waiting

The MSG pin is asserted when there is a message in any of the 2 internal FIFO buffers. This

pin is TTL level and is configurable to be either active high or active low signal.

The Pin shall also be programmable via SPI to remain either active during CS_S once is set

or inactive during CS. If the pin is configured to remain active during CS_S and there is a

message in any of the internal FIFO it remains active even if CS_S is de-asserted. However

if there are no messages in any of the internal 2 FIFOs the pin is forced to inactive state.

4.14.9

Satellite serial data input (MOSI)

The MOSI input takes data from the master microprocessor while CS_S is asserted. The

MSB is the first bit of each word received on MOSI and the LSB is the last bit of each word

received on MOSI. This pin has TTL level compatible input voltages allowing proper

operation with microprocessors using a 3.3 to 5.0 volt supply. MOSI bits layout is provided

here below.

4.14.10

Satellite MOSI bits definition

Table 32. Satellite MOSI bits layout

DATA (12:0)

There is a total of 5 internal registers that are used to configure all of the satellite channels.

These registers are addressed by setting MOSI bit 14 according to this table and by sending

L9654 Datasheet(PDF) 49 Page - STMicroelectronics

L9654 Datasheet(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL