Application hints

TDA7387

10/15

DocID024094 Rev 2

3

Application hints

Refer to Figure 3.

3.1

Biasing and SVR

As shown in Figure 12, all the TDA7387’s main sections, such as Inputs, Outputs AND AC-

GND (pin 16) are internally biased at half supply voltage level (Vs/2), coming from the

Supply Voltage Rejection (SVR) block. In this way no current flows through the internal

feedback network. The AC-GND is common to all the 4 amplifiers and represents the

connection point of all the inverting inputs.

Both individual inputs and AC-GND are connected to Vs/2 (SVR) by means of 100 k



resistors.

To ensure proper operation and high supply voltage rejection, it is of fundamental

importance to provide a good impedance matching between Inputs and AC-GROUND

nominal value and their tolerance should never exceed ± 10 %.

Besides its contribution to the ripple rejection, the SVR capacitor controls the turn ON/OFF

time sequence and, consequently, plays an essential role in the pop optimization during

ON/OFF transients. To conveniently serve both needs, its minimum recommended value

is 10µF.

Figure 12. Input/output biasing.

3.2

Input stage

The TDA7387’s inputs are ground-compatible and can stand very high input signals

(± 8 Vpk) without any performances degradation.

If the standard value for the input capacitors (0.1 µF) is adopted, the low frequency cut-off

turns out to be 16 Hz.