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ES9218PC Datasheet(PDF) 50 Page - ESS Technology,Inc |
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ES9218PC Datasheet(HTML) 50 Page - ESS Technology,Inc |
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50 / 101 page  ES9218P Datasheet December 6, 2018 CONFIDENTIAL ADVANCE INFORMATION 1.8 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 50 Register 10: Master Mode and Sync Configuration (0x0A) Bits [7] [6:5] [4] [3:0] Mnemonic master_mode master_div 128fs_mode lock_speed Default 1’b0 2’b00 1’b0 4’d2 Bit Mnemonic Description [7] master_mode Enables master mode which causes the ES9218P to drive the DATA_CLK and DATA1 signals when in I2S mode. Can also be enabled when in DSD mode to enable DATA_CLK only. • 1’b0: disables master mode (default) • 1’b1: enables master mode [6:5] master_div Sets the frame clock (DATA1) and DATA_CLK frequencies when in master mode. This register is used when in normal synchronous operation. • 2’b00: DATA_CLK frequency = CLK/2 (default) • 2’b01: DATA_CLK frequency = CLK/4 • 2’b10: DATA_CLK frequency = CLK/8 • 2’b11: DATA_CLK frequency = CLK/16 See Master Mode for more details. [4] 128fs_mode Disable ASRC and enables synchronous operation: • 1’b0: disables CLK = 128*FSR mode (default) • 1’b1: enables CLK = 128*FSR mode DATA_CLK and CLK must be synchronous and the audio sample rate must be exactly 128*FSR: ������������������ ������������������ = 128 [3:0] lock_speed Sets the number of audio samples required before the DPLL and ASRC lock to the incoming signal during asynchronous operation. More audio samples give a better initial estimate of the CLK/FSR ratio at the expense of a longer locking interval. • 4’d0: 16384 FS edges • 4’d1: 8192 FS edges • 4’d2: 5461 FS edges (default) • 4’d3: 4096 FS edges • 4’d4: 3276 FS edges • 4’d5: 2730 FS edges • 4’d6: 2340 FS edges • 4’d7: 2048 FS edges • 4’d8: 1820 FS edges • 4’d9: 1638 FS edges • 4’d10: 1489 FS edges • 4’d11: 1365 FS edges • 4’d12: 1260 FS edges • 4’d13: 1170 FS edges • 4’d14: 1092 FS edges • 4’d15: 1024 FS edges |
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