MICRF505BML datasheet(21/27 Pages) MICREL

21 / 27 page

May 13, 2004

M9999-051304

MICRF505

Micrel

Bit Synchronizer

A6..A0

0000110

—

ModclkS2

ModclkS1

ModclkS0

BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111

BitRate_clkS1 BitRate_clkS0

RefClk_K5

RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

A bit synchronizer can be enabled in receive mode by

selecting the synchronous mode (Sync_en=1). The DataClk-

pin will output a clock with twice the frequency of the bit rate

(a bit rate of 20 kbit/sec gives a DataClk of 20 kHz). A received

symbol/bit on DataIXO will be output on rising edge of

DataClk. The micro controller should therefore sample the

symbol/bit on falling edge of DataClk.

The bit synchronizer uses a clock which needs to be pro-

grammed according to the bit rate. The clock frequency

should be 16 times the actual bit rate (a bit rate of 20 kbit/sec

needs a bit synchronizer clock with frequency of 320 kHz).

The clock frequency is set by the following formula:

Refclk_K

BITSYNC_CLK

XCO

()

BITSYNC clkS

where

fBITSYNC_CLK: The bit synchronizer clock fre-

quency

(16 times higher than the bit rate)

fXCO:

Crystal oscillator frequency

Refclk_K:

6 bit divider, values between 1

and 63

BitSync_clkS:

Bit synchronizer setting, values

between 0 and 7

Refclk_K is also used to derive the modulator clock and the

bit rate clock.

At the beginning of a received data package, the bit synchro-

nizer clock frequency is not synchronized to the bit rate.

When these two are maximum offset to each other, it takes 22

bit/symbols before synchronization is achieved.

Transmitter

Power Amplifier

A6..A0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

Load_en

0000001

Modulation1 Modulation0

"0"

RSSI_en

LD_en

PF_FC1

PF_FC0

The maximum output power is approximately 10dBm for a

W load. For maximum output power the load seen by the

PA must be resistive. Higher output power can be obtained by

decreasing the load impedance. However, this will be in

conflict with obtaining impedance match in the LNA. The

output power is programmable in seven steps, with approxi-

mately 3dB between each step. This is controlled by bits PA2

- PA0. PA2 - PA0 = 1 give the maximum output power.

The power amplifier can be turned off in by settingPA2 - PA0

= 0.

For all other combinations the PA is on and has a maximum

power when PA2 - PA0 = 1. The PA has 7 power levels in this

case.

The output power vary about 3dB over power supply 2.0V to

2.5V and about 2dB over temperature –40ºC to +85ºC. The

2nd and 3rd harmonic of the PA are as follows:

2nd harmonic: <-25dBm

3rd harmonic:

<-15dBm

To reduce the emission of harmonics, a LC filter can be added

between the ANT pin and the antenna as shown in Figure 11.

10pF

4.7nH

Pin 5

ANT

Figure 14. LC Filter

This filter is designed for the 915MHz band with 50Ohm

terminations. The component values may have to be tuned to

compensate for layout parasitics. This filter may also in-

crease the receiver selectivity.

MICRF505BML Datasheet(PDF) 21 Page - Micrel Semiconductor

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