WM8714

Production Data

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PD Rev 4.0 November 2004

10

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock

to which all audio data processing is synchronised. This clock is often referred to as the audio

system’s Master Clock. The external master clock can be applied directly through the MCLK input

pin with no configuration necessary for sample rate selection.

Note that on the WM8714, MCLK is used to derive clocks for the DAC path. The DAC path

consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In

a system where there are a number of possible sources for the reference clock it is recommended

that the clock source with the lowest jitter be used to optimise the performance of the DAC.

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Two interface

formats are supported:

•

Right Justified mode

•

I

All formats send the MSB first. The data format is selected with the FORMAT pin. When

FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be

used. When the FORMAT pin is HIGH, I

24-bits may be used. (If the word length shorter than 24-bits is used, the unused bits will be

padded with zeros).

‘Packed’ mode (i.e. only 32 or 48 clocks per LRCLK period) operation is also supported in both

I

length is applied (16 BITCLKS per LRCLK half period), the device auto-detects this mode and

switches to 16-bit data length.

I

The WM8714 supports word lengths of 16-24 bits in I

In I

multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used

as a timing reference to indicate the beginning or end of the data words.

In I

length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word

length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements

are met.

In I

transition. LRCIN is low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

Figure 3 I