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TMUX7413FRRPR Datasheet(PDF) 33 Page - Texas Instruments

Part # TMUX7413FRRPR
Description  TMUX741xF ±60 V Fault-Protected, 1:1 (SPST), 4-Channel Switches With Latch-Up Immunity and 1.8-V Logic
PDF  48 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMUX7413FRRPR Datasheet(HTML) 33 Page - Texas Instruments

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9.3.2.2 Powered-Off Protection
When the supplies of TMUX7411F, TMUX7412F, and TMUX7413F are removed (VDD/ VSS = 0 V or floating), the
source (Sx) pins of the device remain in high impedance (Hi-Z) state, and the device performance remains within
the leakage performance. Powered-off protection minimizes system complexity by removing the need to control
power supply sequencing of the system. The feature prevents errant voltages on the input source pins from
reaching the rest of the system and maintains isolation when the system is powering up. Without powered-off
protection, signals on the input source pins can back-power the supply rails through internal ESD diodes and
cause potential damage to the system.
A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to
±60 V are blocked in the powered-off condition.
9.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
logic signals. The logic inputs are protected against positive faults of up to +44 V in powered-off condition, but do
not offer protection against negative overvoltage condition.
Fail-safe logic also allows the TMUX741xF devices to interface with a voltage greater than VDD during normal
operation to add maximum flexibility in system design. For example, with a VDD of = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 44 V.
9.3.2.4 Overvoltage Protection and Detection
The TMUX7411F, TMUX7412F, and TMUX7413F detect overvoltage inputs by comparing the voltage on a
source pin (Sx) with the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply
voltages by the threshold voltage (VT).
The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source
pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin
(Dx) is left floating when the fault channel is selected by the logic control. For example, if the source voltage
exceeds VDD or VSS, then the drain output is left floating and the circuit connected to the drain pin, such as RL
and CL, determines the final voltage.
9.3.2.5 ESD Protection
All pins on the TMUX7411F, TMUX7412F, and TMUX7413F support HBM ESD protection level up to ±6 kV,
which helps prevent the device from being damaged by ESD events during manufacturing process.
The drain pins (Dx) have internal ESD protection diodes to the supplies VDD and VSS, therefore the voltage at
the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have
specialized ESD protection that allows the signal voltage to reach ±60 V regardless of the supply voltage level.
Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the
device to malfunction if the damage is excessive.
9.3.2.6 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX7411F, TMUX7412F, and TMUX7413F devices, an insulating oxide layer is placed on top of the
silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune
under all circumstances by device construction.
www.ti.com
TMUX7411F, TMUX7412F, TMUX7413F
SCDS404B – MARCH 2021 – REVISED NOVEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: TMUX7411F TMUX7412F TMUX7413F



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