MLP2016WR47M datasheet(14/48 Pages) TOSHIBA

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TC7738WBG

2016-11-17

8.3.4.

Startup sequence

TC7738WBG can change the timing by writing to eFuse when the power supply of each channel turns ON. Delay time

can set maximum SLT6 (3 ms (typ.)) for each channel, assuming that the SLOT time 0.5 ms (typ.) is one step.

The following shows the startup sequence of each power supply of “TC7738WBG-P00”. P00 means the setting code.

(Example) TC7738WBG-P00 setting

SLT0: CH5, CH6, LDO2

SLT1: CH2, CH3, CH4

SLT2: CH1, LDO1

VIN = 3.3 V, VSEL0 = H, MODE_SEL = L, FB1 = L

3.3V (typ.)

2.8V (typ.)

Tss

3.3V

Voltage output of

Default output voltage according to

VSEL0

CH1 (BYPASS-mode) operation start

6ms (typ.)

LDO2 (BYPASS-mode) operation start

3.3V

1.2V

1.8V

0.9V

1.8V

3.3V

CH4 (DC-DC4) operation start

LDO1 operation start

VOUT

ＲＥＳＥＴｎ pin output signal

VIN

CH5 (DC-DC5) operation start

CH6 (DC-DC6) operation start

CH2 (DC-DC2) operation start

CH3 (DC-DC3) operation start

1.9V (typ.)

IC startup

UVLO deacitive detection signal

ＲＥＳＥＴｎ deactive detection signal

SLOT1 SLOT2

SLOT0

0.5ms(typ)

1.0ms(typ)

Note: UVLO deactive detection signal and RESETn deactive detection signal are internal signals.

Figure 8-6

Startup ON sequence (TC7738WBG-P00)

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