STPM34 datasheet(65/121 Pages) STMICROELECTRONICS

65 / 121 page

DS10272 Rev 8

65/121

STPM32, STPM33, STPM34

Theory of operation

121

Interrupt control mask register

Each bit in the status register has a correspondent bit in DSP_IRQ1, DSP_IRQ2 interrupt

mask registers. For each bit set, the relative event detection is output on INT1, INT2 pins

respectively. In the STPM32, DSP_IRQ1 is mapped on INT1 pin only.

Status bits can be monitored by an external microcontroller application, in fact when INTx

pin triggers, the application reads the relative status register content and clears it.

Note:

Power sign status bits generate level interrupts.

8.5

Functional description of communication peripheral

The STPM3x can be interfaced to a control unit through a programmable communication

peripheral which can be:



4-pin SPI



2-pin UART

The serial communication peripherals share same pins so that they cannot be used at the

same time.

Interface selection is implemented through an internal detection system that, at the device

startup, detects which of the two communication interfaces has to be used. This feature

allows communication to be quickly established with minimal initialization.

Auto-detection works at startup, (power-up or EN pin transition from low to high) by

monitoring SCS pin status and automatically selecting the communication interface that

matches the configuration:



If SCS pin is held low the communication method is SPI



If SCS pin is held high the communication interface is UART.

For the communication interface selection the SCS pin must be kept low or high for SPI or

UART selection respectively for at least 125ns after the internal clock signal starts.

According to POR sequence in Figure 28, only after the regulated voltages are OK the

PWR_OK internal signal enables the CLKIN signal to the digital section. After two clock

periods, the digital section sets and locks the interface to the selected type. Note that the

regulated voltages could be ready later than the Vcc minimum threshold of 2.5 V, because

of the capacitance on VDDA and VDDD pins.

Below a timing diagram of startup and interface selection.

Tamper status(1)

Tamper

Tamper or wrong connection

1. Valid for the STPM33 and STPM34 only.

Table 22. Status register (continued)

Bit

Internal signal

Description

STPM34 Datasheet(PDF) 65 Page - STMicroelectronics

STPM34 Datasheet(HTML) 65 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL