ADC14155 datasheet(16/19 Pages) NSC

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Applications Information (Continued)

RP =VRM +VREF /2

RN =VRM −VREF /2

3.0 DIGITAL INPUTS

Digital CMOS compatible inputs consist of CLK+, CLK−,

PD/DCS and CLK_SEL/DF.

3.1 Clock Inputs

The CLK+ and CLK− signals control the timing of the sam-

pling process. The CLK_SEL/DF pin (pin 8) allows the user

to configure the ADC for either differential or single-ended

clock mode (see Section 3.3). The differential mode is rec-

ommended to obtain the best distortion performance. In

differential clock mode, the two clock signals should be

exactly 180˚ out of phase from each other and of the same

amplitude. If a slight degradation in distortion performance is

acceptable, the single-ended clock mode may be used. In

this configuration, the clock signal should be routed to the

CLK+ input and the CLK− input should be tied to AGND in

combination with the correct setting from Table 3.

To achieve the optimum noise performance, the clock inputs

should be driven with a stable, low jitter clock signal in the

range indicated in the Electrical Table with rise and fall times

of TBD ns or less. The trace carrying the clock signal should

be as short as possible and should not cross any other signal

line, analog or digital, not even at 90˚. Figure 4 shows the

recommended differential clock input circuit.

The clock signal also drives an internal state machine. If the

clock is interrupted, or its frequency is too low, the charge on

the internal capacitors can dissipate to the point where the

accuracy of the output data will degrade. This is what limits

the minimum sample rate.

The clock line should be terminated at its source in the

characteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on

setting characteristic impedance.

It is highly desirable that the the source driving the ADC

clock pins only drive that pin. However, if that source is used

to drive other things, each driven pin should be AC termi-

nated with a series RC to ground, such that the resistor value

is equal to the characteristic impedance of the clock line and

the capacitor value is

where t

PD is the signal propagation rate down the clock line,

"L" is the line length and Z

O is the characteristic impedance

of the clock line. This termination should be as close as

possible to the ADC clock pin but beyond it as seen from the

clock source. Typical t

PD is about 150 ps/inch (60 ps/cm) on

FR-4 board material. The units of "L" and t

PD should be the

same (inches or centimeters).

The duty cycle of the clock signal can affect the performance

of the A/D Converter. Because achieving a precise duty

cycle is difficult, the ADC14155 has a Duty Cycle Stabilizer.

It is designed to maintain performance over a clock duty

cycle range of 30% to 70%.

3.2 Power-Down (PD)

Power-down can be enabled through this two-state input pin.

Table 2 shows how to power-down the ADC14155.

TABLE 2. Power Down Selection Table

PD Input Voltage

Power State

Power-down

AGND

The power-down mode allows the user to conserve power

when the converter is not being used. In the power-down

state all bias currents of the analog circuitry, excluding the

reference are shut down which reduces the power consump-

tion to 5 mW with no clock running. The output data pins are

undefined and the data in the pipeline is corrupted while in

the power-down mode.

The Power-down Mode Exit Cycle time is determined by the

value of the capacitors on the V

RP,VRM and VRN reference

bypass pins (pins 43, 44 and 45) and is about 3 ms with the

recommended component values. These capacitors lose

their charge in the power-down mode and must be re-

charged by on-chip circuitry before conversions can be ac-

curate. Smaller capacitor values allow slightly faster recov-

ery from the power down mode, but can result in a reduction

in SNR, SINAD and ENOB performance.

3.3 Clock Mode Select/Data Format (CLK_SEL/DF)

Single-ended versus differential clock mode and output data

format are selectable using this quad-state function pin.

Table 3 shows how to select between the clock modes and

the output data formats.

TABLE 3. Clock Mode and Data Format Selection Table

CLK_SEL/DF

Input Voltage

Clock Mode

Output Data

Format

Differential

2’s Complement

(2/3) * V

Differential

Offset Binary

(1/3) * V

Single-Ended

2’s Complement

AGND

Single-Ended

Offset Binary

4.0 DIGITAL OUTPUTS

Digital outputs consist of the 1.8V CMOS signals D0-D13,

DRDY and OVR.

The ADC14155 has 16 CMOS compatible data output pins:

14 data output bits corresponding to the converted input

value, a DRDY signal that should be used to capture the

output data and an over-range indicator (OVR) which is set

high when the sample amplitude exceeds the 14-bit conver-

sion range. Valid data is present at these outputs while the

PD pins is low.

Data should be captured with the DRDY signal and the rising

edge of the DRDY signal should be used to latch the data.

Depending on the setup and hold time requirements of the

receiving circuit (ASIC), either the rising edge or the falling

edge of the DRDY signal can be used to latch the data.

Generally, rising-edge capture would maximize setup time

with minimal hold time; while falling-edge-capture would

maximize hold time with minimal setup time. However, actual

timing for the falling-edge case depends greatly on the CLK

frequency and both cases also depend on the delays inside

the ASIC. Refer to the AC Electrical Characterisitics table.

Be very careful when driving a high capacitance bus. The

more capacitance the output drivers must charge for each

conversion, the more instantaneous digital current flows

through V

DR and DRGND. These large charging current

spikes can cause on-chip ground noise and couple into the

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