ADC3583 datasheet(69/85 Pages) TI

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9 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Typical Application

A spectrum analyzer is a typical frequency domain application for the ADC358x and its front end circuitry is

very similar to several other systems such as software defined radio (SDR), sonar, radar or communications.

Some applications require frequency coverage including DC or near DC (such as, sonar), so it is included in this

example.

Control

AIN

CLK

VREF

ADC

0.95V

VCM

DB0/1

DCLKIN

DCLK

FCLK

DA0/1

Dig I/F

FPGA

1.2V REF

REFBUF

10 k

0.6V

Device Clock

AMP

CVCM

Low Pass Filter

180nH

100 pF

Glitch Filter

10 uF

NCO

Figure 9-1. Typical configuration for a spectrum analyzer with DC support

9.1.1 Design Requirements

Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in

the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the

input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is

not needed then AC coupling and use of a balun may be more suitable.

The internal reference is used since DC precision is not needed. However the ADC AC performance is highly

dependent on the quality of the external clock source. If in-band interferers can be present then the ADC SFDR

performance will be a key care about as well. A higher ADC sampling rate is desirable in order to relax the

external anti-aliasing filter – an internal decimation filter can be used to reduce the digital output rate afterwards.

Table 9-1. Design key care-abouts

FEATURE

DESCRIPTION

Signal Bandwidth

DC to 20 MHz

Input Driver

Single ended to differential signal conversion and DC coupling

Clock Source

External clock with low jitter

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC358x input full-scale is 3.2 Vpp. When factoring in ~ 1 dB for insertion loss

of the filter, then the amplifier needs to deliver close to 3.6 Vpp. The amplifier distortion performance will degrade

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SBAS873A – FEBRUARY 2021 – REVISED OCTOBER 2022

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