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FS5600 Datasheet(PDF) 85 Page - NXP Semiconductors |
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FS5600 Datasheet(HTML) 85 Page - NXP Semiconductors |
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85 / 111 page ![]() NXP Semiconductors FS5600 Automotive buck regulator and controller with voltage monitors and watchdog timer 18.1.28 STATE register Bit Symbol Description 4 to 0 PMIC_FSM[4:0] Indicates FSM State. 5b'00100 - ABIST 5b'00101 - Power Up 5b'01000 - Deep Fail-Safe 5b'01001 - INIT RUN 5b'01100 - NORMAL 5b'01101 - Thermal Shutdown 5b'10000 - Power Down 5b'10001 - POR Others - Reserved Reset Condition — POR Table 83. STATE register description 18.1.29 ID1 register Bit Symbol Description 13 to 11 FULL_LAYER_REV[2:0] Silicon revision identification 10 to 8 METAL_LAYER_REV[2:0] Silicon revision identification 7 to 4 FAM_ID[3:0] Family Id (1011 for FS56). 4b'1011 — Family Id (1011 for FS56). Reset Condition — POR 3 to 0 DEVICEID[3:0] Device variation identification. Defaulted to 0. Table 84. ID1 register description 19 Typical application curves (VIN = 12 V, Switching Frequency = 450 kHz, Hardware: KITFS5600FRDMEVM, SW1 = 5 V, SW2 = 3.3 V, Temperature = 25 C, SW1 Inductor = 6.8 μH, 14.5 mΩ, SW2 HS FET: BUK9M9R5-40H, SW2 LS FET: BUK9M3R3, SW2 Inductor: 4.7 μH, 7.5 mΩ DCR, unless otherwise noted..) Figure 20. SW1 Soft-start FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022 85 / 111 |
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