PI2DPX2063 datasheet(28/36 Pages) DIODES

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A Product Line of

Diodes Incorporated

PI2DPX2063

July 2022

PI2DPX2063

Document Number DS43839 Rev 2-2

www.diodes.com

BYTE 17

Bit

Type

Power-up Condition

Comment

Reserved

BYTE 18 (DPCD Address 00101h: Lane Count Set)

Bit

Type

Power-up Condition

Comment

LANE_COUNT_SET

Main-Link Lane Count = Value.

Bit<4:0>LANE_COUNT_SET

Three values are supported. All other values are RESERVED.

Note: Because the upstream device is required to set this value within the

MAX_LINK_RATE register (DPCD Address 00001h), there is no power-on

reset default value for this field. It is suggested to program this field to 1h.

(See the Note within the description for the LINK_BW_SET register (DPCD

Address 00100h.)

1h = 1 lane (Lane 0 only)

2h = 2 lanes (Lanes 0 and 1 only)

4h = 4 lanes

A Source device may choose any lane count as long as it does not exceed the

capability of the DPRX.

For DPCD Ver.1.0:

Bits <7:5> = RESERVED. Read all 0’s.

For DPCD Ver.1.1:

Bits <6:5> = RESERVED. Read all 0’s.

Bit 7 = ENHANCED_FRAME_EN

0 = Enhanced Framing symbol sequence is not enabled.

1 = Enhanced Framing symbol sequence for BS and SR is enabled. Appli-

cable to SST-only mode. A DPTX must set this bit to 1 when the DPRX has

the ENHANCED_FRAME_CAP bit in the MAX_LANE_COUNT register

(DPCD Address 00002h, bit 7) set to 1.

BYTE 19 - 30 (Reserved)

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