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SOLOMON
Rev 1.3
10/2002
SSD1905
30
GPIO2 Pulse Delay Register
REG[40h]
Bit
7
6
5
4
3
2
1
0
GPIO2
Delay Bit 7
GPIO2
Delay Bit 6
GPIO2
Delay Bit 5
GPIO2
Delay Bit 4
GPIO2
Delay Bit 3
GPIO2
Delay Bit 2
GPIO2
Delay Bit 1
GPIO2
Delay Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
state
0
0
0
0
0
0
0
0
Bits 7-0
GPIO2 Pulse Delay [7:0]
These bits specify the pulse delay of the GPIO2 signal within a line, in 1 pixel
resolution.
Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bit 3 = 1, REG[10h] bits 1-0 = 10 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions, see Section 10.4.9 “320x240 Sharp
HR-TFT Panel Timing (e.g. LQ039Q2DS01)”.
STN Color Depth Control Register
REG[45h]
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STN Color
Depth
Control
Type
NA
NA
NA
NA
NA
NA
NA
RW
Reset
state
0
0
0
0
0
0
0
0
Bit 0
STN Color Depth control
This bit controls the maximum number of color available for STN panels.
When this bit = 0, it allows maximum 32k color depth.
When this bit = 1, it allows maximum 256k color depth.
Please refer to Table 7-8 :
LCD Bit-per-pixel Selection for the color depth
relationship.
Note
REG[45h] is effective for STN panel only (REG[10h] bits 1:0 = 00).
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