HANBit

HFDOM44KRxxx

URL:www.hbe.co.kr

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HANBit Electronics Co., Ltd.

Rev. 1.0 (December, 2004)

2 Host Read/Write timing

Sym.

Description

Min.

Typ.

Max.

Unit

Td

HD bus asserted from HIOR# / HOE#

10

ns

HD hold time after HIOR# / HOE#

40

70

ns

HD set up time of HIOW# / HWE#

10

ns

HD hold time of HIOW# / HWE#

5

ns

Read HD Valid

Td

Th

(R)

HD write

Th

(W)

Ts

(W)

HIOW#/

HWE#

HIOR#/HOE#

HA

HA Valid

CE[2:1]

3 Flash Read/Write timing

Sym.

Description

Min.

Typ.

Max.

Unit

Flash Read / Write cycle time

100

ns

FD set up time of FWE#

80

ns

FD hold time of FWE#

40

ns

FD set up time of FRD#

10

ns

FD hold time of FRD#

5

ns

REGISTERS

1) Data Register (Address – 1F0h[170h];Offset 0,8,9)

The Data Register is a 16-bit register, and it is used to transfer data blocks between the

CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.The table below

describes the combinations of data register access and is provided to assist in understanding the overlapped Data

Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes

and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for

I/O and Memory cycles.

Note: Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for word (-CE2 = 0

and -CE1 = 0) operations. These accesses are treated as accesses to the Word Data

Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that

can be performed by the socket.