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TNY284 Datasheet(PDF) 2 Page - Power Integrations, Inc.

Part # TNY284
Description  Energy-Efficient, Off-Line Switcher with Line Compensated Overload Power
PDF  26 Pages
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Manufacturer  POWERINT [Power Integrations, Inc.]
Direct Link  http://www.powerint.com
Logo POWERINT - Power Integrations, Inc.

TNY284 Datasheet(HTML) 2 Page - Power Integrations, Inc.

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Rev. G 10/20
2
TNY284-290
www.power.com
Pin Functional Description
DRAIN (D) Pin:
This pin is the power MOSFET drain connection. It provides internal
operating current for both start-up and steady-state operation.
BYPASS/MULTI-FUNCTION (BP/M) Pin:
This pin has multiple functions:
• It is the connection point for an external bypass capacitor for the
internally generated 5.85 V supply.
• It is a mode selector for the current limit value, depending on the
value of the capacitance added. Use of a 0.1 μF capacitor results
in the standard current limit value. Use of a 1 μF capacitor results
in the current limit being reduced to that of the next smaller device
size. Use of a 10 μF capacitor results in the current limit being
increased to that of the next larger device size for TNY285-290.
• It provides a shutdown function. When the current into the bypass
pin exceeds I
SD, the device latches off until the BP/M voltage drops
below 4.9 V, during a power-down or, when the UV function is
employed with external resistors connected to the BP/UV pin, by
taking the UV/EN pin current below I
UV minus the reset hysteresis
(Typ. 18.75 μA). This can be used to provide an output overvolt-
age function with a Zener connected from the BYPASS/MULTI-
FUNCTIONAL pin to a bias winding supply.
Figure 3. Functional Block Diagram.
PI-6639-072115
CLOCK
OSCILLATOR
5.85 V
4.9 V
SOURCE
(S)
S
R
Q
DCMAX
BYPASS/
MULTI-FUNCTION
(BP/M)
+
-
VI
LIMIT
FAULT
PRESENT
CURRENT LIMIT
COMPARATOR
ENABLE
LEADING
EDGE
BLANKING
THERMAL
SHUTDOWN
+
-
DRAIN
(D)
REGULATOR
5.85 V
BYPASS PIN
UNDER-VOLTAGE
1.0 V + VT
ENABLE/
UNDER-
VOLTAGE
(EN/UV)
Q
115 µA
25 µA
LINE UNDERVOLTAGE
RESET
AUTO-
RESTART
COUNTER
JITTER
1.0 V
6.4 V
BYPASS
CAPACITOR
SELECT AND
CURRENT
LIMIT STATE
MACHINE
OVP
LATCH
LINE
COMPENSATION
Figure 4. Pin Configuration.
PI-6577-021015
P Package (DIP-8C)
12 S
11 S
10 S
9 S
8 S
7 S
EN/UV 1
BP/M 2
N/C 3
N/C 4
D 6
K Package
(eSOP-12B)
Exposed Pad (On Bottom)
Internally Connected to
SOURCE Pin
D Package (SO-8C)
EN/UV 1
BP/M 2
D 4
8 S
7 S
6 S
5 S
5 S
7 S
8 S
D 4
BP/M 2
EN/UV 1
6 S



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