XRT84L38 datasheet(9/451 Pages) EXAR

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 253

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 253

Figure 57. Interfacing XRT84L38 to local Terminal Equipment using 16.384Mbit/s Data Bus 254

Figure 58. Timing Diagram of Input signals to the Framer when running at Bit-multiplexed

16.384Mbit/s ...................................................................................................................... 254

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 255

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 255

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 255

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 255

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 256

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 256

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 256

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 256

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 256

Figure 59. Interfacing XRT84L38 to local Terminal Equipment using 16.384Mbit/s Data Bus 257

Figure 60. Timing Diagram of Input signals to the Framer when running at HMVIP 16.384Mbit/s

257

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 258

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 259

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 259

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 259

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 259

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 259

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 260

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 260

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 260

Figure 61. Interfacing XRT84L38 to local Terminal Equipment using H.100 16.384Mbit/s Data Bus

261

Figure 62. Timing Diagram of Input signals to the Framer when running at H.100 16.384Mbit/s .

261

6.0 The E1 Transmit Section ...................................................................................................................... 262

6.1 THE E1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ............................................................... 262

6.1.1 Description of the Transmit Payload Data Input Interface Block ............................................ 262

6.1.2 Brief Discussion of the Transmit Payload Data Input Interface Block Operating at XRT84V24 Com-

patible 2.048Mbit/s mode ................................................................................................................ 262

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 262

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 263

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 264

Figure 63. Interfacing XRT84L38 to local terminal equipment with TxSerClk_n as Transmit Tim-

ing Source ......................................................................................................................... 266

Figure 64. Waveforms of the signals that connect the Transmit Payload Data Input Interface

Block to the local Terminal Equipment with the Transmit Serial clock being the timing

source of the Transmit Section ....................................................................................... 267

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 268

Figure 65. Interfacing XRT84L38 to local terminal equipment with OSCCLK driven divided clock

as transmit timing source ................................................................................................ 269

Figure 66. Waverforms of the signals connecting the Transmit Payload Data Input Interface

block to the local Terminal Equipment with the OSCCLK driven divided clock as the tim-

ing source of the Transmit Section ................................................................................. 270

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 271

Figure 67. Interfacing XRT84L38 to local terminal equipment with recovered receive line clock

as transmit timing source ................................................................................................ 272

6.1.3 Brief Discussion of the Transmit High-Speed Back-Plane Interface ...................................... 273

Figure 68. Waverforms of the signals connecting the Transmit Payload Data input interface

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