LTC3313JVPBF datasheet(20/28 Pages) AD

20 / 28 page

LTC3313

Rev. 0

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APPLICATIONS INFORMATION

See Figure 4 for a recommended PCB layout.

Figure 4. Recommended PCB Layout for the LTC3313

COUT1

COUT2

CIN3

CFF

CIN4

CIN1

CIN5

GND

VIN

GROUND PLANE ON LAYER 2

VOUT

CSS

CC2

CC1

3313 F04

TO VOUT AND GND

REMOTE SENSE

CIN2

Large, switched currents flow in the LTC3313 VIN, SW,

and PGND pins and input capacitors. The loops formed

by the input capacitors should be as small as possible by

placing the capacitors adjacent to the VIN and PGND pins.

Place the input capacitors, inductor, and output capaci-

tors on the same layer of the circuit board. Place a local,

unbroken ground plane under the application circuit on

the layer closest to the surface layer.

The SW node should be as short as possible. Finally,

keep the FB and RT nodes small and away from the noisy

SW node.

High Temperature Considerations

For higher ambient temperatures, care should be taken

in the layout of the PCB to ensure good heat sinking of

the LTC3313. The PGND pins and the exposed pad on the

bottom of the package should be soldered to a ground

plane. This ground should be tied to large copper layers

below with many thermal vias; these layers will spread

heat dissipated by the LTC3313. Placing additional vias

can reduce thermal resistance further. The maximum load

current should be derated as the ambient temperature

approaches the maximum junction rating. Power dissi-

pation within the LTC3313 can be estimated by calculat-

ing the total power loss from an efficiency measurement

and subtracting the inductor loss. The die temperature is

monitored with the SSTT pin.

LTC3313JVPBF Datasheet(PDF) 20 Page - Analog Devices

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