CS5825
Century Semiconductor Inc.
page 3 of 13
PIN DESCRIPTION
Name
Pin
Description
AIP,
AIM
I
LVDS data channel A input. These are differential LVDS inputs for A channel
corresponds to D0, D1, D2, D3, D4, D6, D7. AIP is the positive data input and AIM is the
negative input.
BIP,
BIM
I
LVDS data channel B output. These are differential LVDS inputs for B channel
corresponds to D8, D9, D12, D13, D14, D15, D18.
CIP,
CIM
I
LVDS data channel C output. These are differential LVDS outputs for C channel
corresponds to D19, D20, D21, D22, D24, D25, D26.
DIP,
DIM
I
LVDS data channel C output. These are differential LVDS outputs for D channel
corresponds to D27, D5, D10, D11, D16, D17, D23.
CKIP,
CKIM
I
LVDS clock channel input. These are differential LVDS input for the frame sync clock.
The clock is sent to an on-chip PLL to generate 7X serial clock; An phase aligner is used
to align the deserializer clock.
D0,D1,D2,D3,D4,
D6, D7
O
Parallel data output for LVDS channel A. D[0] is LSB and D[7] is MSB. MSB is shifted in
first.
D8,D9,D12,D13,
D14,D15,D18
O
Parallel data output for LVDS channel B. D[8] is LSB and D[18] is MSB.
D19,D20,D21,D22
,D24,D25,D26
O
Parallel data output for LVDS channel C. D[19] is LSB and D[26] is MSB.
D27,D5,D10,D11,
D16,D17,D23
O
Parallel data output for LVDS channel C. D[19] is LSB and D[23] is MSB.
CLKOUT
O
Parallel data clock output. This clock signal recovered clock for data output reference.
The falling edge should be used as the strobe for the next stage.
SHTDNN
I
Shutdown control (low active). When SHTDNN is low, the internal PLL is put into inhibit
mode and all data outputs are forced low. This also resets all internal registers. For
normal operation, SHTDNN should be set to high.
VDD
P
Positive power supply for TTL outputs. A 3.3V supply should be used.
VSS
P
Negative power supply. Connect to 0V.
LVDS_VDD
P
Positive power supply for LVDS inputs.
LVDS_VSS
P
Negative power supply for LVDS inputs.
PLL_VDD
P
Positive power supply for PLL.
PLL_VSS
P
Negative power supply for PLL.
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