Philips Semiconductors

Product specification

74ABT853

8-bit transceiver with 9-bit parity checker/

generator and flag latch (3-State)

1995 Sep 06

2

PIN DESCRIPTION

SYMBOL

PIN NUMBER

NAME AND FUNCTION

A0 – A7

2, 3, 4, 5, 6, 7, 8, 9

A port 3–State inputs/outputs

B0 – B7

23, 22, 21, 20, 19, 18, 17, 16

B port 3–State inputs/outputs

OEA

1

Enables the A outputs when Low

OEB

14

Enables the B outputs when Low

PARITY

15

Parity output/input

ERROR

10

Error output (open collector)

CLEAR

11

Clears the error flag register when Low

ENABLE

13

Enable input (active-Low)

GND

12

Ground (0V)

24

Positive supply voltage

FUNCTION TABLE

INPUTS

OUTPUTS

MODE

OEB

OEA

An

Σ OF HIGHS

Bn + PARITY

Σ OF HIGHS

An

Bn

PARITY

A data to B bus and generate odd parity output

L

H

Odd

Even

(output)

(input)

An

L

H

H

L

(output)

X

Bn

(input)

(input)

H

H

X

X

Z

Z

Z

A data to B bus and generate inverted parity output

L

L

Odd

Even

(output)

(input)

An

H

L

NOTES:

1. Error checking is detailed in the Error Flag Function Table below.

2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.

ERROR FLAG FUNCTION TABLE

INPUTS

INTERNAL NODE

OUTPUT

MODE

ENABLE

CLEAR

Bn + PARITY

Σ OF HIGHS

POINT ”P”

PRE–STATE

ERRORn–1

ERROR

OUTPUT

Pass

L

L

Odd

Even

H

L

X

H

L

Sample

L

H

Odd

Even

X

H

L

X

H

X

L

H

L

L

Clear

H

L

X

X

X

H

Store

H

H

X

X

L

H

L

H

H

= High voltage level steady state

L

= Low voltage level steady state

X

= Don’t care

Z

= High impedance ”off” state