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74ABT899 Datasheet(PDF) 3 Page - NXP Semiconductors

Part # 74ABT899
Description  9-bit dual latch transceiver with 8-bit parity generator/checker 3-State
PDF  16 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ABT899 Datasheet(HTML) 3 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
1998 Jan 16
3
PIN CONFIGURATION
3
4
5
6
7
8
9
10
11
12
17
18
19
20
21
22
23
24
25
26
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
APAR
B7
B6
B5
B4
B3
B2
B1
B0
LEB
13
16
OEA
SEL
14
15
GND
ERRB
TOP VIEW
1
227
28
ODD/EVEN
ERRA
OEB
VCC
SA00289
PIN DESCRIPTION
SYMBOL
PIN
NUMBER
NAME AND FUNCTION
A0 - A7
4, 5, 6, 7,
8, 9, 10,
11
Latched A bus 3-State inputs/outputs
B0 - B7
19, 20,
21, 22,
23, 24,
25, 26
Latched B bus 3-State inputs/outputs
APAR
12
A bus parity 3-State input
BPAR
18
B bus parity 3-State input
ODD/
EVEN
1
Parity select input (Low for EVEN
parity)
OEA, OEB
13, 27
Output enable inputs (gate A to B,
B to A)
SEL
16
Mode select input (Low for generate)
LEA, LEB
3, 17
Latch enable inputs (transparent High)
ERRA,
ERRB
2, 15
Error signal outputs (active-Low)
GND
14
Ground (0V)
VCC
28
Positive supply voltage
PLCC PIN CONFIGURATION
3
4
5
17
18
28
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
VCC
LEB
16 SEL
15 ERRB
1
2
27
26
ODD/
EVEN
ERRA
OEB
B0
67
8
9
10
11
13
14 GND
OEA
12 APAR
25
B1
B2
B3
B4
B5
B6
B7
24
23
22 21
20
19
SA00291
LOGIC SYMBOL
456
7
8
9
10 11
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
26 25 24 23 22 21 20 19
2
15
3
16
17
1
LEA
SEL
LEB
ODD/EVEN
ERRA
ERRB
12
APAR
BPAR
18
27
13
OEB
OEA
SA00290



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