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Version 1

– December 2022

19/26

4.15 Communication Timing

Parameter

Symbol

Conditions

Min.

Typ. Max.

Units

Comments

SCL clock frequency

fSCL

0

-

1000

kHz

Hold time (repeated)

START condition

tHD;STA

After this period,

the first

clock pulse is

generated

0.24

-

-

µs

LOW period of the

SCL clock

tLOW

0.53

-

-

µs

HIGH period of the

SCL clock

tHIGH

0.26

-

-

µs

SDA hold time

tHD;DAT

0

-

250

ns

Transmitting data

0

-

-

ns

Receiving data

SDA set-up time

tSU;DAT

100

-

-

ns

SCL/SDA rise time

tR

-

-

300

ns

SCL/SDA fall time

tF

-

-

300

ns

SDA valid time

tVD;DAT

-

-

0.9

µs

Set-up time for a

repeated START

condition

tSU;STA

0.26

-

-

µs

Set-up time for STOP

condition

tSU;STO

0.26

-

-

µs

Capacitive load on bus

line

CB

-

-

400

pF

Low level input voltage

VIL

0

-

0.3xVD

D

V

High level input

voltage

VIH

0.7xVDD

-

1xVDD

V

Low level output

voltage

VOL

3 mA sink current

-

-

0.4

V

Table

23.

Timing

specifications

for

I2C

communication,

valid

for

T =

−40 °C … 125 °C &

VDD = VDDmin

… VDDmax. The nomenclature above is according to the I2C (UM10204, Rev. 6, April 4, 2014).

[2]

Figure 4. Timing diagram for digital input/output pads. SDA directions are seen from the sensor. Bold

SDA lines are controlled by the sensor, plain SDA lines are controlled by the micro-controller. Note that

SDA valid read time is triggered by falling edge of preceding toggle.

SCL

70%

30%

tLOW

1/fSCL

tHIGH

tR

tF

SDA

70%

30%

tSU;DAT

tHD;DAT

DATA IN

tR

SDA

70%

30%

DATA OUT

tVD;DAT

tF