Philips Semiconductors

Product specification

74ALS109A

Dual J-K positive edge triggered flip-flop

with set and reset

2

1991 Feb 08

853–1275 01670

DESCRIPTION

The 74ALS109A is a dual positive edge-triggered JK-type flip-flop

featuring individual J, K, clock, set, and reset inputs; also true and

complementary outputs. Set (SD) and reset (RD) are asynchronous

active-Low inputs and operate independently of the clock (CP) input.

The J and K are edge-triggered inputs which control the state

changes of the flip-flops as described in the function table. Clock

triggering occurs at a voltage level and is not directly related to the

transition time of the positive-going pulse. The J and K inputs must

be stable just one setup time prior to the Low-to-High transition of

the clock for predictable operation. The JK design allows operation

as a D flip-flop by tying J and K inputs together. Although the clock

input is level sensitive, the positive transition of the clock pulse

between the 0.8V and 2.0V levels should be equal to or less than

the clock to output delay time for reliable operation.

TYPE

TYPICAL

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS109A

150MHz

3.0mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

DRAWING

NUMBER

16-pin plastic DIP

74ALS109AN

SOT38-4

16-pin plastic SO

74ALS109AD

SOT109-1

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q0

CP1

SD1

Q1

K1

RD1

J1

RD0

J0

Q0

K0

CP0

SD0

9

8

GND

Q1

SF00135

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

J0, J1

J inputs

1.0/2.0

20

µA/0.2mA

K0, K1

K inputs

1.0/2.0

20

µA/0.2mA

CP0, CP1

Clock inputs (active rising edge)

1.0/2.0

20

µA/0.2mA

SD0, SD1

Set inputs (active-Low)

1.0/4.0

20

µA/0.4mA

RD0, RD1

Reset inputs (active-Low)

1.0/4.0

20

µA/0.4mA

Q0, Q1, Q0, Q1

Data outputs

20/80

0.4mA/8mA

NOTE:

One (1.0) ALS unit load is defined as: 20

µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

J1

J0

Q0 Q0 Q1 Q1

GND = Pin 8

K1

K0

2 14

3 13

6

7

10

9

CP0

SD0

RD0

CP1

SD1

RD1

4

5

1

12

11

15

SF00136

IEC/IEEE SYMBOL

SF00137

7

2

4

3

1

5

14

12

13

15

11

6

10

9

1J

C1

1K

R

S

2J

C2

2K

R

S