Philips Semiconductors

Product specification

74ALS164

8-bit serial-in parallel-out shift register

1991 Feb 08

3

LOGIC DIAGRAM

DQ

RD

Q0

1

Dsa

Dsb

2

CP

MR

3

8

9

GND = Pin 7

DQ

RD

Q1

4

DQ

RD

Q2

5

DQ

RD

Q3

6

DQ

RD

Q4

10

DQ

RD

Q5

11

DQ

RD

Q6

12

DQ

RD

Q7

13

SF00715

CP

CP

CP

CP

CP

CP

CP

CP

MODE SELECT FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

MR

CP

Dsa

Dsb

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

OPERATING MODE

L

X

X

X

L

L

L

L

L

L

L

L

Reset (Clear)

H

↑

l

l

L

q0

q1

q2

q3

q4

q5

q6

H

↑

l

h

L

q0

q1

q2

q3

q4

q5

q6

Shift

H

↑

h

l

L

q0

q1

q2

q3

q4

q5

q6

Shift

H

↑

h

h

H

q0

q1

q2

q3

q4

q5

q6

NOTES:

H = High voltage level

h

= High voltage level one setup time prior to the Low-to-High clock transition

L

= Low voltage level

l

= Low voltage level one setup time prior to the Low-to-High clock transition

qn = Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.

X = Don’t care

↑ = Low-to-High clock transition

APPLICATION

The 74ALS164 can be cascaded to form synchronous shift registers of longer length.

Here, two devices are combined to form a 16-bit shift register.

CLEAR

CLOCK

DATA

ENABLE

Dsa

Dsb

Dsa

Dsb

CP

MR

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9 D10 D11 D12 D13 D14 D15

CP

MR

H

74ALS164

74ALS164

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

SC00063