Philips Semiconductors

Product specification

74ALS377

Octal D flip-flop with enable

2

1991 Feb 08

853–1399 01670

FEATURES

DESCRIPTION

The 74ALS377 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered clock (CP)

input loads all flip-flops simultaneously when the Enable (E) is Low.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition, is transferred to

the corresponding flip-flop’s Q output. The E input must be stable

one setup time prior to the Low-to-High clock transition for

predictable operation.

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS377

95MHz

15mA

PIN CONFIGURATION

20

19

18

17

16

15

14

13

12

10

11

9

8

7

6

5

4

3

2

1

Q7

D7

D6

Q6

Q5

D5

D4

Q4

CP

Q0

D0

D1

Q1

Q2

D2

D3

Q3

GND

E

SF00350

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

DRAWING

NUMBER

20-pin plastic DIP

74ALS377N

SOT146-1

20-pin plastic SOL

74ALS377D

SOT163-1

20-pin plastic SSOP

Type II

74ALS377DB

SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D7

Data inputs

1.0/2.0

20

µA/0.2mA

CP

Clock pulse input (active rising edge)

1.0/1.0

20

µA/0.1mA

E

Latch enable input

1.0/1.0

20

µA/0.1mA

Q0 – Q7

Data outputs

130/240

2.6mA/24mA

NOTE:

One (1.0) ALS unit load is defined as: 20

µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

SF00351

3

4

7

8

13

14

18

17

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

2

5

6

9

12

15

16

19

1

11

E

CP

GND = Pin 10

IEC/IEEE SYMBOL

SF00352

1

32

4

5

7

6

8

9

G1

11

1C2

13

12

14

15

17

16

18

19

2D