Philips Semiconductors

Product specification

74ALS573B/74ALS574A

Latch/flip-flop

1991 Feb 08

4

LOGIC DIAGRAM – 74ALS573B

GND = Pin 10

D0

D

E

Q

Q0

2

19

D1

D

E

Q

Q1

3

18

D2

D

E

Q

Q2

4

17

D3

D

E

Q

Q3

5

16

D4

D

E

Q

Q4

6

15

D5

D

E

Q

Q5

7

14

D6

D

E

Q

Q6

8

13

D7

D

E

Q

Q7

9

12

11

E

SC00109

1

OE

FUNCTION TABLE – 74ALS573B

INPUTS

OUTPUTS

INTERNAL

OPERATING MODE

OE

E

Dn

REGISTER

Q0 – Q7

OPERATING MODE

L

H

L

L

L

Enable and read register

L

H

H

H

H

Enable and read register

L

↓

l

L

L

Latch and read register

L

↓

h

H

H

Latch and read register

L

L

X

NC

NC

Hold

H

L

X

NC

Z

Disable outputs

H

H

Dn

Dn

Z

Disable outputs

H = High-voltage level

h

= High state must be present one setup time before the High-to-Low enable transition

L

= Low-voltage level

l

= Low state must be present one setup time before the High-to-Low enable transition

NC= No change

X = Don’t care

Z = High impedance “off” state

↓ = High-to-Low enable transition

LOGIC DIAGRAM – 74ALS574A

VCC = Pin 20

D0

D

CP Q

Q0

2

19

D1

D

CP Q

Q1

3

18

D2

D

CP Q

Q2

4

17

D3

D

CP Q

Q3

5

16

D4

D

CP Q

Q4

6

15

D5

D

CP Q

Q5

7

14

D6

D

CP Q

Q6

8

13

D7

D

CP Q

Q7

9

12

11

OE

CP

GND = Pin 10

SC00110

1