MCT8317A datasheet(151/161 Pages) TI1

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11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize parasitic inductance and allow the bulk capacitor to

deliver high current.

Small-value capacitors should be ceramic, and placed closely to device pins.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the

device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to

reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the I2 × RDS(on) heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise

into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching.

Figure 11-1 shows a layout example for the MCT8317A. Also, for layout example, refer to MCT8317A EVM.

www.ti.com

MCT8317A

SLLSFQ2 – JANUARY 2023

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MCT8317A Datasheet(PDF) 151 Page - Texas Instruments