MCT8317A datasheet(105/161 Pages) TI1

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8.7.1.13 REF_PROFILES2 Register (Offset = 9Ch) [Reset = X]

REF_PROFILES2 is shown in Figure 8-61 and described in Table 8-23.

Return to the Table 8-9.

Figure 8-61. REF_PROFILES2 Register

PARITY

DUTY_A

DUTY_B

R/W-0h

R/W-X

DUTY_B

DUTY_C

R/W-X

DUTY_C

DUTY_D

R/W-X

DUTY_D

DUTY_E

R/W-X

R/W-0h

Table 8-23. REF_PROFILES2 Register Field Descriptions

Bit

Field

Type

Reset

Description

PARITY

R/W

Parity bit

30-28

DUTY_A

R/W

3 LSB bits for Duty Cycle A Duty Cycle A (%) = {(DUTY_A/255)*100}

27-20

DUTY_B

R/W

Duty_B Configuration Duty Cycle B (%) = {(DUTY_B/255)*100}

19-12

DUTY_C

R/W

Duty_C Configuration Duty Cycle C (%) = {(DUTY_C/255)*100}

11-4

DUTY_D

R/W

Duty_D Configuration Duty Cycle D (%) = {(DUTY_D/255)*100}

3-0

DUTY_E

R/W

4 MSB bits for Duty Cycle E Duty Cycle E (%) = {(DUTY_E/

255)*100}

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MCT8317A

SLLSFQ2 – JANUARY 2023

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