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MCT8317A Datasheet(PDF) 135 Page - Texas Instruments |
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MCT8317A Datasheet(HTML) 135 Page - Texas Instruments |
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135 / 161 page  8.8.4.1 DEVICE_CTRL Register (Offset = E8h) [Reset = 00000000h] DEVICE_CTRL is shown in Figure 8-79 and described in Table 8-55. Return to the Table 8-53. Device Control Parameters Figure 8-79. DEVICE_CTRL Register 31 30 29 28 27 26 25 24 RESERVED SPEED_CTRL W-0h W-0h 23 22 21 20 19 18 17 16 SPEED_CTRL W-0h 15 14 13 12 11 10 9 8 OVERRIDE RESERVED W-0h R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 8-55. DEVICE_CTRL Register Field Descriptions Bit Field Type Reset Description 31 RESERVED W 0h Reserved 30-16 SPEED_CTRL W 0h Digital speed command (SPEED_CTRL (%) = SPEED_CTRL/32767 * 100%) 15 OVERRIDE W 0h Speed input select for I2C vs speed pin 0h = SPEED_CMD using Analog/Freq/PWM mode 1h = SPEED_CMD using SPD_CTRL[14:0] 14-0 RESERVED R 0h Reserved 8.8.5 Algorithm_Variables Registers Table 8-56 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 8-56 should be considered as reserved locations and the register contents should not be modified. Table 8-56. ALGORITHM_VARIABLES Registers Offset Acronym Register Name Section 40Ch INPUT_DUTY Input Duty Cycle Section 8.8.5.1 512h CURRENT_DUTY Current Duty Cycle Section 8.8.5.2 522h SET_DUTY Set Duty Cycle Section 8.8.5.3 5CEh MOTOR_SPEED_PU Motor Speed in PU Section 8.8.5.4 714h DC_BUS_POWER_PU DC Bus Power in PU Section 8.8.5.5 Complex bit access types are encoded to fit into small table cells. Table 8-57 shows the codes that are used for access types in this section. Table 8-57. Algorithm_Variables Access Type Codes Access Type Code Description Read Type R R Read www.ti.com MCT8317A SLLSFQ2 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: MCT8317A |
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