MCT8317A datasheet(132/161 Pages) TI1

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8.8.2.3 SYS_STATUS3 Register (Offset = ECh) [Reset = 00000000h]

SYS_STATUS3 is shown in Figure 8-77 and described in Table 8-49.

Return to the Table 8-45.

Status of various system and motor parameters

Figure 8-77. SYS_STATUS3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

DC_BUS_CURR

DC_BATT_POW

R-0h

Table 8-49. SYS_STATUS3 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

DC_BUS_CURR

DC bus current (/256 to get DC bus current in A)

15-0

DC_BATT_POW

Battery (input) power (/64 to get battery power in W)

8.8.3 Algo_Control Registers

Table 8-50 lists the memory-mapped registers for the Algo_Control registers. All register offset addresses not

listed in Table 8-50 should be considered as reserved locations and the register contents should not be modified.

Table 8-50. ALGO_CONTROL Registers

Offset

Acronym

Section

E6h

ALGO_CTRL1

Algorithm Control Parameters

Section 8.8.3.1

Complex bit access types are encoded to fit into small table cells. Table 8-51 shows the codes that are used for

access types in this section.

Table 8-51. Algo_Control Access Type Codes

Access Type

Code

Description

Write Type

Write

Reset or Default Value

-n

Value after reset or the default

value

MCT8317A

SLLSFQ2 – JANUARY 2023

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