LM3489MM datasheet(14/15 Pages) NSC

14 / 15 page

Design Information (Continued)

INTERFACING WITH THE ENABLE PIN

The enable pin is internally pulled high with clamping at 8V

typical. For normal operation this pin should be left open. To

disable the device, the enable pin should be connected to

ground externally. If an external voltage source is applied to

this pin for enable control, the applied voltage should not

exceed the maximum operating voltage level specified in this

datasheet, i.e. 5.5V. For most applications, an open drain or

open collector transistor can be used to short this pin to

ground to shutdown the device .

PCB Layout

The PCB board layout is very important in all switching

regulator designs. Poor layout can cause switching noise

into the feedback signal and generate EMI problems. For

minimal inductance, the wires indicated by heavy lines in

schematic diagram should be as wide and short as possible.

Keep the ground pin of the input capacitor as close as

possible to the anode of the catch diode. This path carries a

large AC current. The switching node, the node with the

diode cathode, inductor and FET drain should be kept short.

This node is one of the main sources for radiated EMI since

it sees a large AC voltage at the switching frequency. It is

always a good practice to use a ground plane in the design,

particularly for high current applications.

The two ground pins, PGND and GND, should be connected

by as short a trace as possible. They can be connected

underneath the device. These pins are resistively connected

internally by approximately 50

Ω. The ground pins should be

tied to the ground plane, or to a large ground trace in close

proximity to both the FB divider and C

OUT grounds.

The gate pin of the external PFET should be located close to

the PGATE pin. However, if a very small FET is used, a

resistor may be required between PGATE pin and the gate of

the PFET to reduce high frequency ringing. Since this resis-

tor will slow down the PFET’s rise time, the current limit

blanking time should be taken into consideration (refer to

Current Limiting Operation). The feedback voltage signal line

can be sensitive to noise. Avoid inductive coupling with the

inductor or the switching node. The FB trace should be kept

away from those areas. Also, the orientation of the inductor

can contribute un-wanted noise coupling to the FB path. If

noise problems are observed it may be worth trying a differ-

ent orientation of the inductor and select the best for final

component placement.

20186953

FIGURE 7. Typical Application Schematic for VOUT = 3.3V/500mA

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