IC89C52(51)A

Integrated CircuitSolution Inc.

21

MC008-0C 11/27/2001

Figure 18. Erase Timing Waveform

Figure 19. External Clock Drive Waveform

Figure 20. AC Test Point

Note:

1.AC inputs during testing are driven at Vcc-0.5v for logic “1” and 0.45V for logic “0”.

Timing measurements are made at Vih min for logic “1” and max for logic “0”.

0.45V

Vcc — 0.5V

0.7Vcc

0.2Vcc — 0.1

Vcc - 0.5V

0.45V

0.2Vcc + 0.9V

0.2Vcc - 0.1V

P2.4-P2.0

P1.7-P1.0

PROG

VPP

ADDRESS IN

ERASE

SETUP CYCLE

ERASE CYCLE

ERASE VERIFY

SETUP CYCLE

ERASE

VERIFY CYCLE

DATA OUT

P0

P2.6

(Command Setup)

P2.7(OE)

D0H

20H

A0H