9

Rev. A

05/02/06

IS93C56A

IS93C66A

AC WAVEFORMS

FIGURE 2. SYNCHRONOUS DATA TIMING

FIGURE 3. READ CYCLE TIMING

CS

0

Dm

D0

11

0

An

A0

*

Notes:

To determine address bits An-A0 and data bits Dm-Do, see Instruction Set for the specific device.

T

CS

SK

(READ)

(WRITE)

(WRALL)

(ERASE)

(ERAL)

STATUS VALID