Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

2

April 4, 1989

853–0354 96224

FEATURES

DESCRIPTION

The functional characteristics of the 74F194 4-Bit Bidirectional Shift

Register are indicated in the Logic Diagram and Function Table. The

register is fully synchronous, with all operations taking place in less

than 9ns (typical) for 74F, making the device especially useful for

implementing very high speed CPUs, or for memory buffer registers.

The 74F194 design has special logic features which increase the

range of application. The synchronous operation of the device is

determined by two Mode Select inputs, S0 and S1. As shown in the

Mode Select-Function Table, data can be entered and shifted from

left to right (shift right, Q0

→Q1, etc.), or right to left (shift left,

Q3

→Q2, etc.), or parallel data can be entered, loading all 4 bits of

the register simultaneously. When both S0 and S1 are Low, existing

data is retained in a hold (do nothing) mode. The first and last

multistage shift right or shift left data transfers without interfering

with parallel load operation. Mode Select and data inputs on the

74F194 are edge-triggered, responding only to the Low-to-High

transition of the Clock (CP). Therefore, the only timing restriction is

that the Mode Select and selected data inputs must be stable one

setup time prior to the Low-to-High transition of the clock pulse.

Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data

only the recommended setup and hold times, with respect to the

clock rising edge, are observed. The four Parallel Data inputs

(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when

S0 and S1 are High is transferred to the Q0–Q3 outputs

respectively, following the next Low-to-High transition of the clock.

When Low, the asynchronous Master Reset (MR) overrides all other

input conditions and forces the Q outputs Low.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q3

CP

S1

Q2

Q0

Q1

MR

D3

D0

D1

D2

9

8

GND

S0

SF00167

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F194

150MHz

33mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F194N

SOT38-4

16-pin plastic SO

N74F194D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

D0–D3

Parallel data inputs

1.0/1.0

20

µA/0.6mA

Serial data input (Shift Right)

1.0/1.0

20

µA/0.6mA

Serial data input (Shift Left)

1.0/1.0

20

µA/0.6mA

S0, S1

Mode Select inputs

1.0/1.0

20

µA/0.6mA

CP

Clock Pulse input (active rising edge)

1.0/1.0

20

µA/0.6mA

MR

Asynchronous master Reset input (Active Low)

1.0/1.0

20

µA/0.6mA

Q0–Q3

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.